9ns: change parsecmd()'s size arg's type to size_t
[akaros.git] / kern / drivers / net / mlx4 / main.c
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * OpenIB.org BSD license below:
12  *
13  *     Redistribution and use in source and binary forms, with or
14  *     without modification, are permitted provided that the following
15  *     conditions are met:
16  *
17  *      - Redistributions of source code must retain the above
18  *        copyright notice, this list of conditions and the following
19  *        disclaimer.
20  *
21  *      - Redistributions in binary form must reproduce the above
22  *        copyright notice, this list of conditions and the following
23  *        disclaimer in the documentation and/or other materials
24  *        provided with the distribution.
25  *
26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33  * SOFTWARE.
34  */
35
36 #include <linux_compat.h>
37 #include <linux/mlx4/device.h>
38 #include <linux/mlx4/doorbell.h>
39
40 #include "mlx4.h"
41 #include "fw.h"
42 #include "icm.h"
43
44 MODULE_AUTHOR("Roland Dreier");
45 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
46 MODULE_LICENSE("Dual BSD/GPL");
47 MODULE_VERSION(DRV_VERSION);
48
49 struct workqueue_struct *mlx4_wq;
50
51 #ifdef CONFIG_MLX4_DEBUG
52
53 int mlx4_debug_level = 0;
54 module_param_named(debug_level, mlx4_debug_level, int, 0644);
55 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
56
57 #endif /* CONFIG_MLX4_DEBUG */
58
59 #ifdef CONFIG_PCI_MSI
60
61 static int msi_x = 1;
62 module_param(msi_x, int, 0444);
63 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
64
65 #else /* CONFIG_PCI_MSI */
66
67 #define msi_x (0)
68
69 #endif /* CONFIG_PCI_MSI */
70
71 static uint8_t num_vfs[3] = {0, 0, 0};
72 static int num_vfs_argc;
73 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
74 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
75                           "num_vfs=port1,port2,port1+2");
76
77 static uint8_t probe_vf[3] = {0, 0, 0};
78 static int probe_vfs_argc;
79 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
80 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
81                            "probe_vf=port1,port2,port1+2");
82
83 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
84 module_param_named(log_num_mgm_entry_size,
85                         mlx4_log_num_mgm_entry_size, int, 0444);
86 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
87                                          " of qp per mcg, for example:"
88                                          " 10 gives 248.range: 7 <="
89                                          " log_num_mgm_entry_size <= 12."
90                                          " To activate device managed"
91                                          " flow steering when available, set to -1");
92
93 static bool enable_64b_cqe_eqe = true;
94 module_param(enable_64b_cqe_eqe, bool, 0444);
95 MODULE_PARM_DESC(enable_64b_cqe_eqe,
96                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
97
98 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
99                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
100                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
101
102 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
103
104 static char mlx4_version[] =
105         DRV_NAME ": Mellanox ConnectX core driver v"
106         DRV_VERSION " (" DRV_RELDATE ")\n";
107
108 static struct mlx4_profile default_profile = {
109         .num_qp         = 1 << 18,
110         .num_srq        = 1 << 16,
111         .rdmarc_per_qp  = 1 << 4,
112         .num_cq         = 1 << 16,
113         .num_mcg        = 1 << 13,
114         .num_mpt        = 1 << 19,
115         .num_mtt        = 1 << 20, /* It is really num mtt segements */
116 };
117
118 static struct mlx4_profile low_mem_profile = {
119         .num_qp         = 1 << 17,
120         .num_srq        = 1 << 6,
121         .rdmarc_per_qp  = 1 << 4,
122         .num_cq         = 1 << 8,
123         .num_mcg        = 1 << 8,
124         .num_mpt        = 1 << 9,
125         .num_mtt        = 1 << 7,
126 };
127
128 static int log_num_mac = 7;
129 module_param_named(log_num_mac, log_num_mac, int, 0444);
130 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
131
132 static int log_num_vlan;
133 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
134 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
135 /* Log2 max number of VLANs per ETH port (0-7) */
136 #define MLX4_LOG_NUM_VLANS 7
137 #define MLX4_MIN_LOG_NUM_VLANS 0
138 #define MLX4_MIN_LOG_NUM_MAC 1
139
140 static bool use_prio;
141 module_param_named(use_prio, use_prio, bool, 0444);
142 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
143
144 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
145 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
146 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
147
148 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
149 static int arr_argc = 2;
150 module_param_array(port_type_array, int, &arr_argc, 0444);
151 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
152                                 "1 for IB, 2 for Ethernet");
153
154 struct mlx4_port_config {
155         struct list_head list;
156         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
157         struct pci_device *pdev;
158 };
159
160 static atomic_t pf_loading = ATOMIC_INIT(0);
161
162 int mlx4_check_port_params(struct mlx4_dev *dev,
163                            enum mlx4_port_type *port_type)
164 {
165         int i;
166
167         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
168                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
169                         if (port_type[i] != port_type[i + 1]) {
170                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
171                                 return -EINVAL;
172                         }
173                 }
174         }
175
176         for (i = 0; i < dev->caps.num_ports; i++) {
177                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
178                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
179                                  i + 1);
180                         return -EINVAL;
181                 }
182         }
183         return 0;
184 }
185
186 static void mlx4_set_port_mask(struct mlx4_dev *dev)
187 {
188         int i;
189
190         for (i = 1; i <= dev->caps.num_ports; ++i)
191                 dev->caps.port_mask[i] = dev->caps.port_type[i];
192 }
193
194 enum {
195         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
196 };
197
198 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
199 {
200         int err = 0;
201         struct mlx4_func func;
202
203         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
204                 err = mlx4_QUERY_FUNC(dev, &func, 0);
205                 if (err) {
206                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
207                         return err;
208                 }
209                 dev_cap->max_eqs = func.max_eq;
210                 dev_cap->reserved_eqs = func.rsvd_eqs;
211                 dev_cap->reserved_uars = func.rsvd_uars;
212                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
213         }
214         return err;
215 }
216
217 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
218 {
219         struct mlx4_caps *dev_cap = &dev->caps;
220
221         /* FW not supporting or cancelled by user */
222         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
223             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
224                 return;
225
226         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
227          * When FW has NCSI it may decide not to report 64B CQE/EQEs
228          */
229         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
230             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
231                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
232                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
233                 return;
234         }
235
236         if (cache_line_size() == 128 || cache_line_size() == 256) {
237                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
238                 /* Changing the real data inside CQE size to 32B */
239                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
240                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
241
242                 if (mlx4_is_master(dev))
243                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
244         } else {
245                 if (cache_line_size() != 32  && cache_line_size() != 64)
246                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
247                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
248                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
249         }
250 }
251
252 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
253                           struct mlx4_port_cap *port_cap)
254 {
255         dev->caps.vl_cap[port]      = port_cap->max_vl;
256         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
257         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
258         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
259         /* set gid and pkey table operating lengths by default
260          * to non-sriov values
261          */
262         dev->caps.gid_table_len[port]  = port_cap->max_gids;
263         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
264         dev->caps.port_width_cap[port] = port_cap->max_port_width;
265         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
266         dev->caps.def_mac[port]        = port_cap->def_mac;
267         dev->caps.supported_type[port] = port_cap->supported_port_types;
268         dev->caps.suggested_type[port] = port_cap->suggested_type;
269         dev->caps.default_sense[port] = port_cap->default_sense;
270         dev->caps.trans_type[port]          = port_cap->trans_type;
271         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
272         dev->caps.wavelength[port]     = port_cap->wavelength;
273         dev->caps.trans_code[port]     = port_cap->trans_code;
274
275         return 0;
276 }
277
278 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
279                          struct mlx4_port_cap *port_cap)
280 {
281         int err = 0;
282
283         err = mlx4_QUERY_PORT(dev, port, port_cap);
284
285         if (err)
286                 mlx4_err(dev, "QUERY_PORT command failed.\n");
287
288         return err;
289 }
290
291 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
292 {
293         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
294                 return;
295
296         if (mlx4_is_mfunc(dev)) {
297                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
298                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
299                 return;
300         }
301
302         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
303                 mlx4_dbg(dev,
304                          "Keep FCS is not supported - Disabling Ignore FCS");
305                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
306                 return;
307         }
308 }
309
310 #define MLX4_A0_STEERING_TABLE_SIZE     256
311 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
312 {
313         int err;
314         int i;
315
316         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
317         if (err) {
318                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
319                 return err;
320         }
321         mlx4_dev_cap_dump(dev, dev_cap);
322
323         if (dev_cap->min_page_sz > PAGE_SIZE) {
324                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
325                          dev_cap->min_page_sz, PAGE_SIZE);
326                 return -ENODEV;
327         }
328         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
329                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
330                          dev_cap->num_ports, MLX4_MAX_PORTS);
331                 return -ENODEV;
332         }
333
334         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
335                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
336                          dev_cap->uar_size,
337                          (unsigned long long)
338                          pci_resource_len(dev->persist->pdev, 2));
339                 return -ENODEV;
340         }
341
342         dev->caps.num_ports          = dev_cap->num_ports;
343         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
344         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
345                                       dev->caps.num_sys_eqs :
346                                       MLX4_MAX_EQ_NUM;
347         for (i = 1; i <= dev->caps.num_ports; ++i) {
348                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
349                 if (err) {
350                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
351                         return err;
352                 }
353         }
354
355         dev->caps.uar_page_size      = PAGE_SIZE;
356         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
357         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
358         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
359         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
360         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
361         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
362         dev->caps.max_wqes           = dev_cap->max_qp_sz;
363         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
364         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
365         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
366         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
367         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
368         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
369         /*
370          * Subtract 1 from the limit because we need to allocate a
371          * spare CQE so the HCA HW can tell the difference between an
372          * empty CQ and a full CQ.
373          */
374         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
375         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
376         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
377         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
378         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
379
380         /* The first 128 UARs are used for EQ doorbells */
381         dev->caps.reserved_uars      = MAX_T(int, 128,
382                                                     dev_cap->reserved_uars);
383         dev->caps.reserved_pds       = dev_cap->reserved_pds;
384         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
385                                         dev_cap->reserved_xrcds : 0;
386         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
387                                         dev_cap->max_xrcds : 0;
388         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
389
390         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
391         dev->caps.page_size_cap      = ~(uint32_t) (dev_cap->min_page_sz - 1);
392         dev->caps.flags              = dev_cap->flags;
393         dev->caps.flags2             = dev_cap->flags2;
394         dev->caps.bmme_flags         = dev_cap->bmme_flags;
395         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
396         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
397         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
398         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
399
400         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
401         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
402                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
403         /* Don't do sense port on multifunction devices (for now at least) */
404         if (mlx4_is_mfunc(dev))
405                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
406
407         if (mlx4_low_memory_profile()) {
408                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
409                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
410         } else {
411                 dev->caps.log_num_macs  = log_num_mac;
412                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
413         }
414
415         for (i = 1; i <= dev->caps.num_ports; ++i) {
416                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
417                 if (dev->caps.supported_type[i]) {
418                         /* if only ETH is supported - assign ETH */
419                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
420                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
421                         /* if only IB is supported, assign IB */
422                         else if (dev->caps.supported_type[i] ==
423                                  MLX4_PORT_TYPE_IB)
424                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
425                         else {
426                                 /* if IB and ETH are supported, we set the port
427                                  * type according to user selection of port type;
428                                  * if user selected none, take the FW hint */
429                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
430                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
431                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
432                                 else
433                                         dev->caps.port_type[i] = port_type_array[i - 1];
434                         }
435                 }
436                 /*
437                  * Link sensing is allowed on the port if 3 conditions are true:
438                  * 1. Both protocols are supported on the port.
439                  * 2. Different types are supported on the port
440                  * 3. FW declared that it supports link sensing
441                  */
442                 mlx4_priv(dev)->sense.sense_allowed[i] =
443                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
444                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
445                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
446
447                 /*
448                  * If "default_sense" bit is set, we move the port to "AUTO" mode
449                  * and perform sense_port FW command to try and set the correct
450                  * port type from beginning
451                  */
452                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
453                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
454                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
455                         mlx4_SENSE_PORT(dev, i, &sensed_port);
456                         if (sensed_port != MLX4_PORT_TYPE_NONE)
457                                 dev->caps.port_type[i] = sensed_port;
458                 } else {
459                         dev->caps.possible_type[i] = dev->caps.port_type[i];
460                 }
461
462                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
463                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
464                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
465                                   i, 1 << dev->caps.log_num_macs);
466                 }
467                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
468                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
469                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
470                                   i, 1 << dev->caps.log_num_vlans);
471                 }
472         }
473
474         dev->caps.max_counters = 1 << LOG2_UP(dev_cap->max_counters);
475
476         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
477         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
478                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
479                 (1 << dev->caps.log_num_macs) *
480                 (1 << dev->caps.log_num_vlans) *
481                 dev->caps.num_ports;
482         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
483
484         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
485             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
486                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
487         else
488                 dev->caps.dmfs_high_rate_qpn_base =
489                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
490
491         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
492             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
493                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
494                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
495                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
496         } else {
497                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
498                 dev->caps.dmfs_high_rate_qpn_base =
499                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
500                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
501         }
502
503         dev->caps.rl_caps = dev_cap->rl_caps;
504
505         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
506                 dev->caps.dmfs_high_rate_qpn_range;
507
508         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
509                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
510                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
511                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
512
513         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
514
515         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
516                 if (dev_cap->flags &
517                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
518                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
519                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
520                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
521                 }
522
523                 if (dev_cap->flags2 &
524                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
525                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
526                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
527                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
528                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
529                 }
530         }
531
532         if ((dev->caps.flags &
533             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
534             mlx4_is_master(dev))
535                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
536
537         if (!mlx4_is_slave(dev)) {
538                 mlx4_enable_cqe_eqe_stride(dev);
539                 dev->caps.alloc_res_qp_mask =
540                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
541                         MLX4_RESERVE_A0_QP;
542
543                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
544                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
545                         mlx4_warn(dev, "Old device ETS support detected\n");
546                         mlx4_warn(dev, "Consider upgrading device FW.\n");
547                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
548                 }
549
550         } else {
551                 dev->caps.alloc_res_qp_mask = 0;
552         }
553
554         mlx4_enable_ignore_fcs(dev);
555
556         return 0;
557 }
558
559 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
560                                        enum pci_bus_speed *speed,
561                                        enum pcie_link_width *width)
562 {
563         uint32_t lnkcap1, lnkcap2;
564         int err1, err2;
565
566 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
567
568         *speed = PCI_SPEED_UNKNOWN;
569         *width = PCIE_LNK_WIDTH_UNKNOWN;
570
571         err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
572                                           &lnkcap1);
573         err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
574                                           &lnkcap2);
575         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
576                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
577                         *speed = PCIE_SPEED_8_0GT;
578                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
579                         *speed = PCIE_SPEED_5_0GT;
580                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
581                         *speed = PCIE_SPEED_2_5GT;
582         }
583         if (!err1) {
584                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
585                 if (!lnkcap2) { /* pre-r3.0 */
586                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
587                                 *speed = PCIE_SPEED_5_0GT;
588                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
589                                 *speed = PCIE_SPEED_2_5GT;
590                 }
591         }
592
593         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
594                 return err1 ? err1 :
595                         err2 ? err2 : -EINVAL;
596         }
597         return 0;
598 }
599
600 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
601 {
602         enum pcie_link_width width, width_cap;
603         enum pci_bus_speed speed, speed_cap;
604         int err;
605
606 #define PCIE_SPEED_STR(speed) \
607         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
608          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
609          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
610          "Unknown")
611
612         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
613         if (err) {
614                 mlx4_warn(dev,
615                           "Unable to determine PCIe device BW capabilities\n");
616                 return;
617         }
618
619         err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
620         if (err || speed == PCI_SPEED_UNKNOWN ||
621             width == PCIE_LNK_WIDTH_UNKNOWN) {
622                 mlx4_warn(dev,
623                           "Unable to determine PCI device chain minimum BW\n");
624                 return;
625         }
626
627         if (width != width_cap || speed != speed_cap)
628                 mlx4_warn(dev,
629                           "PCIe BW is different than device's capability\n");
630
631         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
632                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
633         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
634                   width, width_cap);
635         return;
636 }
637
638 /*The function checks if there are live vf, return the num of them*/
639 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
640 {
641         struct mlx4_priv *priv = mlx4_priv(dev);
642         struct mlx4_slave_state *s_state;
643         int i;
644         int ret = 0;
645
646         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
647                 s_state = &priv->mfunc.master.slave_state[i];
648                 if (s_state->active && s_state->last_cmd !=
649                     MLX4_COMM_CMD_RESET) {
650                         mlx4_warn(dev, "%s: slave: %d is still active\n",
651                                   __func__, i);
652                         ret++;
653                 }
654         }
655         return ret;
656 }
657
658 int mlx4_get_parav_qkey(struct mlx4_dev *dev, uint32_t qpn, uint32_t *qkey)
659 {
660         uint32_t qk = MLX4_RESERVED_QKEY_BASE;
661
662         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
663             qpn < dev->phys_caps.base_proxy_sqpn)
664                 return -EINVAL;
665
666         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
667                 /* tunnel qp */
668                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
669         else
670                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
671         *qkey = qk;
672         return 0;
673 }
674 EXPORT_SYMBOL(mlx4_get_parav_qkey);
675
676 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
677 {
678         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
679
680         if (!mlx4_is_master(dev))
681                 return;
682
683         priv->virt2phys_pkey[slave][port - 1][i] = val;
684 }
685 EXPORT_SYMBOL(mlx4_sync_pkey_table);
686
687 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
688 {
689         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
690
691         if (!mlx4_is_master(dev))
692                 return;
693
694         priv->slave_node_guids[slave] = guid;
695 }
696 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
697
698 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
699 {
700         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
701
702         if (!mlx4_is_master(dev))
703                 return 0;
704
705         return priv->slave_node_guids[slave];
706 }
707 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
708
709 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
710 {
711         struct mlx4_priv *priv = mlx4_priv(dev);
712         struct mlx4_slave_state *s_slave;
713
714         if (!mlx4_is_master(dev))
715                 return 0;
716
717         s_slave = &priv->mfunc.master.slave_state[slave];
718         return !!s_slave->active;
719 }
720 EXPORT_SYMBOL(mlx4_is_slave_active);
721
722 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
723                                        struct mlx4_dev_cap *dev_cap,
724                                        struct mlx4_init_hca_param *hca_param)
725 {
726         dev->caps.steering_mode = hca_param->steering_mode;
727         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
728                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
729                 dev->caps.fs_log_max_ucast_qp_range_size =
730                         dev_cap->fs_log_max_ucast_qp_range_size;
731         } else
732                 dev->caps.num_qp_per_mgm =
733                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
734
735         mlx4_dbg(dev, "Steering mode is: %s\n",
736                  mlx4_steering_mode_str(dev->caps.steering_mode));
737 }
738
739 static int mlx4_slave_cap(struct mlx4_dev *dev)
740 {
741         int                        err;
742         uint32_t                           page_size;
743         struct mlx4_dev_cap        dev_cap;
744         struct mlx4_func_cap       func_cap;
745         struct mlx4_init_hca_param hca_param;
746         uint8_t                    i;
747
748         memset(&hca_param, 0, sizeof(hca_param));
749         err = mlx4_QUERY_HCA(dev, &hca_param);
750         if (err) {
751                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
752                 return err;
753         }
754
755         /* fail if the hca has an unknown global capability
756          * at this time global_caps should be always zeroed
757          */
758         if (hca_param.global_caps) {
759                 mlx4_err(dev, "Unknown hca global capabilities\n");
760                 return -ENOSYS;
761         }
762
763         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
764
765         dev->caps.hca_core_clock = hca_param.hca_core_clock;
766
767         memset(&dev_cap, 0, sizeof(dev_cap));
768         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
769         err = mlx4_dev_cap(dev, &dev_cap);
770         if (err) {
771                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
772                 return err;
773         }
774
775         err = mlx4_QUERY_FW(dev);
776         if (err)
777                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
778
779         page_size = ~dev->caps.page_size_cap + 1;
780         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
781         if (page_size > PAGE_SIZE) {
782                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
783                          page_size, PAGE_SIZE);
784                 return -ENODEV;
785         }
786
787         /* slave gets uar page size from QUERY_HCA fw command */
788         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
789
790         /* TODO: relax this assumption */
791         if (dev->caps.uar_page_size != PAGE_SIZE) {
792                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
793                          dev->caps.uar_page_size, PAGE_SIZE);
794                 return -ENODEV;
795         }
796
797         memset(&func_cap, 0, sizeof(func_cap));
798         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
799         if (err) {
800                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
801                          err);
802                 return err;
803         }
804
805         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
806             PF_CONTEXT_BEHAVIOUR_MASK) {
807                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
808                          func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
809                 return -ENOSYS;
810         }
811
812         dev->caps.num_ports             = func_cap.num_ports;
813         dev->quotas.qp                  = func_cap.qp_quota;
814         dev->quotas.srq                 = func_cap.srq_quota;
815         dev->quotas.cq                  = func_cap.cq_quota;
816         dev->quotas.mpt                 = func_cap.mpt_quota;
817         dev->quotas.mtt                 = func_cap.mtt_quota;
818         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
819         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
820         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
821         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
822         dev->caps.num_eqs               = func_cap.max_eq;
823         dev->caps.reserved_eqs          = func_cap.reserved_eq;
824         dev->caps.reserved_lkey         = func_cap.reserved_lkey;
825         dev->caps.num_pds               = MLX4_NUM_PDS;
826         dev->caps.num_mgms              = 0;
827         dev->caps.num_amgms             = 0;
828
829         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
830                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
831                          dev->caps.num_ports, MLX4_MAX_PORTS);
832                 return -ENODEV;
833         }
834
835         dev->caps.qp0_qkey = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
836                                       MEM_WAIT);
837         dev->caps.qp0_tunnel = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
838                                         MEM_WAIT);
839         dev->caps.qp0_proxy = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
840                                        MEM_WAIT);
841         dev->caps.qp1_tunnel = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
842                                         MEM_WAIT);
843         dev->caps.qp1_proxy = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
844                                        MEM_WAIT);
845
846         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
847             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
848             !dev->caps.qp0_qkey) {
849                 err = -ENOMEM;
850                 goto err_mem;
851         }
852
853         for (i = 1; i <= dev->caps.num_ports; ++i) {
854                 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
855                 if (err) {
856                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
857                                  i, err);
858                         goto err_mem;
859                 }
860                 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
861                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
862                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
863                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
864                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
865                 dev->caps.port_mask[i] = dev->caps.port_type[i];
866                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
867                 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
868                                                     &dev->caps.gid_table_len[i],
869                                                     &dev->caps.pkey_table_len[i]))
870                         goto err_mem;
871         }
872
873         if (dev->caps.uar_page_size * (dev->caps.num_uars -
874                                        dev->caps.reserved_uars) >
875                                        pci_resource_len(dev->persist->pdev,
876                                                         2)) {
877                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
878                          dev->caps.uar_page_size * dev->caps.num_uars,
879                          (unsigned long long)
880                          pci_resource_len(dev->persist->pdev, 2));
881                 goto err_mem;
882         }
883
884         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
885                 dev->caps.eqe_size   = 64;
886                 dev->caps.eqe_factor = 1;
887         } else {
888                 dev->caps.eqe_size   = 32;
889                 dev->caps.eqe_factor = 0;
890         }
891
892         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
893                 dev->caps.cqe_size   = 64;
894                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
895         } else {
896                 dev->caps.cqe_size   = 32;
897         }
898
899         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
900                 dev->caps.eqe_size = hca_param.eqe_size;
901                 dev->caps.eqe_factor = 0;
902         }
903
904         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
905                 dev->caps.cqe_size = hca_param.cqe_size;
906                 /* User still need to know when CQE > 32B */
907                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
908         }
909
910         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
911         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
912
913         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
914         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
915                  hca_param.rss_ip_frags ? "on" : "off");
916
917         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
918             dev->caps.bf_reg_size)
919                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
920
921         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
922                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
923
924         return 0;
925
926 err_mem:
927         kfree(dev->caps.qp0_qkey);
928         kfree(dev->caps.qp0_tunnel);
929         kfree(dev->caps.qp0_proxy);
930         kfree(dev->caps.qp1_tunnel);
931         kfree(dev->caps.qp1_proxy);
932         dev->caps.qp0_qkey = NULL;
933         dev->caps.qp0_tunnel = NULL;
934         dev->caps.qp0_proxy = NULL;
935         dev->caps.qp1_tunnel = NULL;
936         dev->caps.qp1_proxy = NULL;
937
938         return err;
939 }
940
941 static void mlx4_request_modules(struct mlx4_dev *dev)
942 {
943         int port;
944         int has_ib_port = false;
945         int has_eth_port = false;
946 #define EN_DRV_NAME     "mlx4_en"
947 #define IB_DRV_NAME     "mlx4_ib"
948
949         for (port = 1; port <= dev->caps.num_ports; port++) {
950                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
951                         has_ib_port = true;
952                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
953                         has_eth_port = true;
954         }
955
956 #if 0 // AKAROS_PORT
957         if (has_eth_port)
958                 request_module_nowait(EN_DRV_NAME);
959         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
960                 request_module_nowait(IB_DRV_NAME);
961 #endif
962 }
963
964 /*
965  * Change the port configuration of the device.
966  * Every user of this function must hold the port mutex.
967  */
968 int mlx4_change_port_types(struct mlx4_dev *dev,
969                            enum mlx4_port_type *port_types)
970 {
971         int err = 0;
972         int change = 0;
973         int port;
974
975         for (port = 0; port <  dev->caps.num_ports; port++) {
976                 /* Change the port type only if the new type is different
977                  * from the current, and not set to Auto */
978                 if (port_types[port] != dev->caps.port_type[port + 1])
979                         change = 1;
980         }
981         if (change) {
982                 mlx4_unregister_device(dev);
983                 for (port = 1; port <= dev->caps.num_ports; port++) {
984                         mlx4_CLOSE_PORT(dev, port);
985                         dev->caps.port_type[port] = port_types[port - 1];
986                         err = mlx4_SET_PORT(dev, port, -1);
987                         if (err) {
988                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
989                                          port);
990                                 goto out;
991                         }
992                 }
993                 mlx4_set_port_mask(dev);
994                 err = mlx4_register_device(dev);
995                 if (err) {
996                         mlx4_err(dev, "Failed to register device\n");
997                         goto out;
998                 }
999                 mlx4_request_modules(dev);
1000         }
1001
1002 out:
1003         return err;
1004 }
1005
1006 static ssize_t show_port_type(struct device *dev,
1007                               struct device_attribute *attr,
1008                               char *buf)
1009 {
1010         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1011                                                    port_attr);
1012         struct mlx4_dev *mdev = info->dev;
1013         char type[8];
1014
1015         sprintf(type, "%s",
1016                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1017                 "ib" : "eth");
1018         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1019                 sprintf(buf, "auto (%s)\n", type);
1020         else
1021                 sprintf(buf, "%s\n", type);
1022
1023         return strlen(buf);
1024 }
1025
1026 static ssize_t set_port_type(struct device *dev,
1027                              struct device_attribute *attr,
1028                              const char *buf, size_t count)
1029 {
1030         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1031                                                    port_attr);
1032         struct mlx4_dev *mdev = info->dev;
1033         struct mlx4_priv *priv = mlx4_priv(mdev);
1034         enum mlx4_port_type types[MLX4_MAX_PORTS];
1035         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1036         static DEFINE_MUTEX(set_port_type_mutex);
1037         int i;
1038         int err = 0;
1039
1040         qlock(&set_port_type_mutex);
1041
1042         if (!strcmp(buf, "ib\n"))
1043                 info->tmp_type = MLX4_PORT_TYPE_IB;
1044         else if (!strcmp(buf, "eth\n"))
1045                 info->tmp_type = MLX4_PORT_TYPE_ETH;
1046         else if (!strcmp(buf, "auto\n"))
1047                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
1048         else {
1049                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1050                 err = -EINVAL;
1051                 goto err_out;
1052         }
1053
1054         mlx4_stop_sense(mdev);
1055         qlock(&priv->port_mutex);
1056         /* Possible type is always the one that was delivered */
1057         mdev->caps.possible_type[info->port] = info->tmp_type;
1058
1059         for (i = 0; i < mdev->caps.num_ports; i++) {
1060                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1061                                         mdev->caps.possible_type[i+1];
1062                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1063                         types[i] = mdev->caps.port_type[i+1];
1064         }
1065
1066         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1067             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1068                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1069                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1070                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1071                                 err = -EINVAL;
1072                         }
1073                 }
1074         }
1075         if (err) {
1076                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1077                 goto out;
1078         }
1079
1080         mlx4_do_sense_ports(mdev, new_types, types);
1081
1082         err = mlx4_check_port_params(mdev, new_types);
1083         if (err)
1084                 goto out;
1085
1086         /* We are about to apply the changes after the configuration
1087          * was verified, no need to remember the temporary types
1088          * any more */
1089         for (i = 0; i < mdev->caps.num_ports; i++)
1090                 priv->port[i + 1].tmp_type = 0;
1091
1092         err = mlx4_change_port_types(mdev, new_types);
1093
1094 out:
1095         mlx4_start_sense(mdev);
1096         qunlock(&priv->port_mutex);
1097 err_out:
1098         qunlock(&set_port_type_mutex);
1099
1100         return err ? err : count;
1101 }
1102
1103 enum ibta_mtu {
1104         IB_MTU_256  = 1,
1105         IB_MTU_512  = 2,
1106         IB_MTU_1024 = 3,
1107         IB_MTU_2048 = 4,
1108         IB_MTU_4096 = 5
1109 };
1110
1111 static inline int int_to_ibta_mtu(int mtu)
1112 {
1113         switch (mtu) {
1114         case 256:  return IB_MTU_256;
1115         case 512:  return IB_MTU_512;
1116         case 1024: return IB_MTU_1024;
1117         case 2048: return IB_MTU_2048;
1118         case 4096: return IB_MTU_4096;
1119         default: return -1;
1120         }
1121 }
1122
1123 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1124 {
1125         switch (mtu) {
1126         case IB_MTU_256:  return  256;
1127         case IB_MTU_512:  return  512;
1128         case IB_MTU_1024: return 1024;
1129         case IB_MTU_2048: return 2048;
1130         case IB_MTU_4096: return 4096;
1131         default: return -1;
1132         }
1133 }
1134
1135 static ssize_t show_port_ib_mtu(struct device *dev,
1136                              struct device_attribute *attr,
1137                              char *buf)
1138 {
1139         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1140                                                    port_mtu_attr);
1141         struct mlx4_dev *mdev = info->dev;
1142
1143         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1144                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1145
1146         sprintf(buf, "%d\n",
1147                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1148         return strlen(buf);
1149 }
1150
1151 static ssize_t set_port_ib_mtu(struct device *dev,
1152                              struct device_attribute *attr,
1153                              const char *buf, size_t count)
1154 {
1155         panic("Disabled");
1156 #if 0 // AKAROS_PORT
1157         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1158                                                    port_mtu_attr);
1159         struct mlx4_dev *mdev = info->dev;
1160         struct mlx4_priv *priv = mlx4_priv(mdev);
1161         int err, port, mtu, ibta_mtu = -1;
1162
1163         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1164                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1165                 return -EINVAL;
1166         }
1167
1168         err = kstrtoint(buf, 0, &mtu);
1169         if (!err)
1170                 ibta_mtu = int_to_ibta_mtu(mtu);
1171
1172         if (err || ibta_mtu < 0) {
1173                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1174                 return -EINVAL;
1175         }
1176
1177         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1178
1179         mlx4_stop_sense(mdev);
1180         qlock(&priv->port_mutex);
1181         mlx4_unregister_device(mdev);
1182         for (port = 1; port <= mdev->caps.num_ports; port++) {
1183                 mlx4_CLOSE_PORT(mdev, port);
1184                 err = mlx4_SET_PORT(mdev, port, -1);
1185                 if (err) {
1186                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1187                                  port);
1188                         goto err_set_port;
1189                 }
1190         }
1191         err = mlx4_register_device(mdev);
1192 err_set_port:
1193         qunlock(&priv->port_mutex);
1194         mlx4_start_sense(mdev);
1195         return err ? err : count;
1196 #endif
1197 }
1198
1199 int mlx4_bond(struct mlx4_dev *dev)
1200 {
1201         int ret = 0;
1202         struct mlx4_priv *priv = mlx4_priv(dev);
1203
1204         qlock(&priv->bond_mutex);
1205
1206         if (!mlx4_is_bonded(dev))
1207                 ret = mlx4_do_bond(dev, true);
1208         else
1209                 ret = 0;
1210
1211         qunlock(&priv->bond_mutex);
1212         if (ret)
1213                 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1214         else
1215                 mlx4_dbg(dev, "Device is bonded\n");
1216         return ret;
1217 }
1218 EXPORT_SYMBOL_GPL(mlx4_bond);
1219
1220 int mlx4_unbond(struct mlx4_dev *dev)
1221 {
1222         int ret = 0;
1223         struct mlx4_priv *priv = mlx4_priv(dev);
1224
1225         qlock(&priv->bond_mutex);
1226
1227         if (mlx4_is_bonded(dev))
1228                 ret = mlx4_do_bond(dev, false);
1229
1230         qunlock(&priv->bond_mutex);
1231         if (ret)
1232                 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1233         else
1234                 mlx4_dbg(dev, "Device is unbonded\n");
1235         return ret;
1236 }
1237 EXPORT_SYMBOL_GPL(mlx4_unbond);
1238
1239
1240 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1241 {
1242         uint8_t port1 = v2p->port1;
1243         uint8_t port2 = v2p->port2;
1244         struct mlx4_priv *priv = mlx4_priv(dev);
1245         int err;
1246
1247         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1248                 return -ENOTSUPP;
1249
1250         qlock(&priv->bond_mutex);
1251
1252         /* zero means keep current mapping for this port */
1253         if (port1 == 0)
1254                 port1 = priv->v2p.port1;
1255         if (port2 == 0)
1256                 port2 = priv->v2p.port2;
1257
1258         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1259             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1260             (port1 == 2 && port2 == 1)) {
1261                 /* besides boundary checks cross mapping makes
1262                  * no sense and therefore not allowed */
1263                 err = -EINVAL;
1264         } else if ((port1 == priv->v2p.port1) &&
1265                  (port2 == priv->v2p.port2)) {
1266                 err = 0;
1267         } else {
1268                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1269                 if (!err) {
1270                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1271                                  port1, port2);
1272                         priv->v2p.port1 = port1;
1273                         priv->v2p.port2 = port2;
1274                 } else {
1275                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1276                 }
1277         }
1278
1279         qunlock(&priv->bond_mutex);
1280         return err;
1281 }
1282 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1283
1284 static int mlx4_load_fw(struct mlx4_dev *dev)
1285 {
1286         struct mlx4_priv *priv = mlx4_priv(dev);
1287         int err;
1288
1289         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1290                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1291         if (!priv->fw.fw_icm) {
1292                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1293                 return -ENOMEM;
1294         }
1295
1296         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1297         if (err) {
1298                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1299                 goto err_free;
1300         }
1301
1302         err = mlx4_RUN_FW(dev);
1303         if (err) {
1304                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1305                 goto err_unmap_fa;
1306         }
1307
1308         return 0;
1309
1310 err_unmap_fa:
1311         mlx4_UNMAP_FA(dev);
1312
1313 err_free:
1314         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1315         return err;
1316 }
1317
1318 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, uint64_t cmpt_base,
1319                                 int cmpt_entry_sz)
1320 {
1321         struct mlx4_priv *priv = mlx4_priv(dev);
1322         int err;
1323         int num_eqs;
1324
1325         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1326                                   cmpt_base +
1327                                   ((uint64_t) (MLX4_CMPT_TYPE_QP *
1328                                                cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1329                                   cmpt_entry_sz, dev->caps.num_qps,
1330                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1331                                   0, 0);
1332         if (err)
1333                 goto err;
1334
1335         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1336                                   cmpt_base +
1337                                   ((uint64_t) (MLX4_CMPT_TYPE_SRQ *
1338                                                cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1339                                   cmpt_entry_sz, dev->caps.num_srqs,
1340                                   dev->caps.reserved_srqs, 0, 0);
1341         if (err)
1342                 goto err_qp;
1343
1344         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1345                                   cmpt_base +
1346                                   ((uint64_t) (MLX4_CMPT_TYPE_CQ *
1347                                                cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1348                                   cmpt_entry_sz, dev->caps.num_cqs,
1349                                   dev->caps.reserved_cqs, 0, 0);
1350         if (err)
1351                 goto err_srq;
1352
1353         num_eqs = dev->phys_caps.num_phys_eqs;
1354         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1355                                   cmpt_base +
1356                                   ((uint64_t) (MLX4_CMPT_TYPE_EQ *
1357                                                cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1358                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1359         if (err)
1360                 goto err_cq;
1361
1362         return 0;
1363
1364 err_cq:
1365         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1366
1367 err_srq:
1368         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1369
1370 err_qp:
1371         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1372
1373 err:
1374         return err;
1375 }
1376
1377 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1378                          struct mlx4_init_hca_param *init_hca,
1379                          uint64_t icm_size)
1380 {
1381         struct mlx4_priv *priv = mlx4_priv(dev);
1382         uint64_t aux_pages;
1383         int num_eqs;
1384         int err;
1385
1386         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1387         if (err) {
1388                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1389                 return err;
1390         }
1391
1392         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1393                  (unsigned long long) icm_size >> 10,
1394                  (unsigned long long) aux_pages << 2);
1395
1396         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1397                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1398         if (!priv->fw.aux_icm) {
1399                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1400                 return -ENOMEM;
1401         }
1402
1403         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1404         if (err) {
1405                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1406                 goto err_free_aux;
1407         }
1408
1409         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1410         if (err) {
1411                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1412                 goto err_unmap_aux;
1413         }
1414
1415
1416         num_eqs = dev->phys_caps.num_phys_eqs;
1417         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1418                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1419                                   num_eqs, num_eqs, 0, 0);
1420         if (err) {
1421                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1422                 goto err_unmap_cmpt;
1423         }
1424
1425         /*
1426          * Reserved MTT entries must be aligned up to a cacheline
1427          * boundary, since the FW will write to them, while the driver
1428          * writes to all other MTT entries. (The variable
1429          * dev->caps.mtt_entry_sz below is really the MTT segment
1430          * size, not the raw entry size)
1431          */
1432         dev->caps.reserved_mtts =
1433                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1434                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1435
1436         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1437                                   init_hca->mtt_base,
1438                                   dev->caps.mtt_entry_sz,
1439                                   dev->caps.num_mtts,
1440                                   dev->caps.reserved_mtts, 1, 0);
1441         if (err) {
1442                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1443                 goto err_unmap_eq;
1444         }
1445
1446         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1447                                   init_hca->dmpt_base,
1448                                   dev_cap->dmpt_entry_sz,
1449                                   dev->caps.num_mpts,
1450                                   dev->caps.reserved_mrws, 1, 1);
1451         if (err) {
1452                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1453                 goto err_unmap_mtt;
1454         }
1455
1456         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1457                                   init_hca->qpc_base,
1458                                   dev_cap->qpc_entry_sz,
1459                                   dev->caps.num_qps,
1460                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1461                                   0, 0);
1462         if (err) {
1463                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1464                 goto err_unmap_dmpt;
1465         }
1466
1467         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1468                                   init_hca->auxc_base,
1469                                   dev_cap->aux_entry_sz,
1470                                   dev->caps.num_qps,
1471                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1472                                   0, 0);
1473         if (err) {
1474                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1475                 goto err_unmap_qp;
1476         }
1477
1478         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1479                                   init_hca->altc_base,
1480                                   dev_cap->altc_entry_sz,
1481                                   dev->caps.num_qps,
1482                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1483                                   0, 0);
1484         if (err) {
1485                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1486                 goto err_unmap_auxc;
1487         }
1488
1489         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1490                                   init_hca->rdmarc_base,
1491                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1492                                   dev->caps.num_qps,
1493                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1494                                   0, 0);
1495         if (err) {
1496                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1497                 goto err_unmap_altc;
1498         }
1499
1500         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1501                                   init_hca->cqc_base,
1502                                   dev_cap->cqc_entry_sz,
1503                                   dev->caps.num_cqs,
1504                                   dev->caps.reserved_cqs, 0, 0);
1505         if (err) {
1506                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1507                 goto err_unmap_rdmarc;
1508         }
1509
1510         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1511                                   init_hca->srqc_base,
1512                                   dev_cap->srq_entry_sz,
1513                                   dev->caps.num_srqs,
1514                                   dev->caps.reserved_srqs, 0, 0);
1515         if (err) {
1516                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1517                 goto err_unmap_cq;
1518         }
1519
1520         /*
1521          * For flow steering device managed mode it is required to use
1522          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1523          * required, but for simplicity just map the whole multicast
1524          * group table now.  The table isn't very big and it's a lot
1525          * easier than trying to track ref counts.
1526          */
1527         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1528                                   init_hca->mc_base,
1529                                   mlx4_get_mgm_entry_size(dev),
1530                                   dev->caps.num_mgms + dev->caps.num_amgms,
1531                                   dev->caps.num_mgms + dev->caps.num_amgms,
1532                                   0, 0);
1533         if (err) {
1534                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1535                 goto err_unmap_srq;
1536         }
1537
1538         return 0;
1539
1540 err_unmap_srq:
1541         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1542
1543 err_unmap_cq:
1544         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1545
1546 err_unmap_rdmarc:
1547         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1548
1549 err_unmap_altc:
1550         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1551
1552 err_unmap_auxc:
1553         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1554
1555 err_unmap_qp:
1556         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1557
1558 err_unmap_dmpt:
1559         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1560
1561 err_unmap_mtt:
1562         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1563
1564 err_unmap_eq:
1565         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1566
1567 err_unmap_cmpt:
1568         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1569         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1570         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1571         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1572
1573 err_unmap_aux:
1574         mlx4_UNMAP_ICM_AUX(dev);
1575
1576 err_free_aux:
1577         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1578
1579         return err;
1580 }
1581
1582 static void mlx4_free_icms(struct mlx4_dev *dev)
1583 {
1584         struct mlx4_priv *priv = mlx4_priv(dev);
1585
1586         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1587         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1588         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1589         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1590         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1591         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1592         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1593         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1594         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1595         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1596         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1597         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1598         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1599         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1600
1601         mlx4_UNMAP_ICM_AUX(dev);
1602         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1603 }
1604
1605 static void mlx4_slave_exit(struct mlx4_dev *dev)
1606 {
1607         struct mlx4_priv *priv = mlx4_priv(dev);
1608
1609         qlock(&priv->cmd.slave_cmd_mutex);
1610         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1611                           MLX4_COMM_TIME))
1612                 mlx4_warn(dev, "Failed to close slave function\n");
1613         qunlock(&priv->cmd.slave_cmd_mutex);
1614 }
1615
1616 static int map_bf_area(struct mlx4_dev *dev)
1617 {
1618         panic("Disabled");
1619 #if 0 // AKAROS_PORT
1620         struct mlx4_priv *priv = mlx4_priv(dev);
1621         resource_size_t bf_start;
1622         resource_size_t bf_len;
1623         int err = 0;
1624
1625         if (!dev->caps.bf_reg_size)
1626                 return -ENXIO;
1627
1628         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1629                         (dev->caps.num_uars << PAGE_SHIFT);
1630         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1631                         (dev->caps.num_uars << PAGE_SHIFT);
1632         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1633         if (!priv->bf_mapping)
1634                 err = -ENOMEM;
1635
1636         return err;
1637 #endif
1638 }
1639
1640 static void unmap_bf_area(struct mlx4_dev *dev)
1641 {
1642         panic("Disabled");
1643 #if 0 // AKAROS_PORT
1644         if (mlx4_priv(dev)->bf_mapping)
1645                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1646 #endif
1647 }
1648
1649 uint64_t mlx4_read_clock(struct mlx4_dev *dev)
1650 {
1651         uint32_t clockhi, clocklo, clockhi1;
1652         uint64_t cycles;
1653         int i;
1654         struct mlx4_priv *priv = mlx4_priv(dev);
1655
1656         for (i = 0; i < 10; i++) {
1657                 clockhi = swab32(read32(priv->clock_mapping));
1658                 clocklo = swab32(read32(priv->clock_mapping + 4));
1659                 clockhi1 = swab32(read32(priv->clock_mapping));
1660                 if (clockhi == clockhi1)
1661                         break;
1662         }
1663
1664         cycles = (uint64_t) clockhi << 32 | (uint64_t) clocklo;
1665
1666         return cycles;
1667 }
1668 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1669
1670
1671 static int map_internal_clock(struct mlx4_dev *dev)
1672 {
1673         struct mlx4_priv *priv = mlx4_priv(dev);
1674
1675         priv->clock_mapping =
1676                 ioremap(pci_resource_start(dev->persist->pdev,
1677                                            priv->fw.clock_bar) +
1678                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1679
1680         if (!priv->clock_mapping)
1681                 return -ENOMEM;
1682
1683         return 0;
1684 }
1685
1686 static void unmap_internal_clock(struct mlx4_dev *dev)
1687 {
1688         struct mlx4_priv *priv = mlx4_priv(dev);
1689
1690         if (priv->clock_mapping)
1691                 iounmap(priv->clock_mapping);
1692 }
1693
1694 static void mlx4_close_hca(struct mlx4_dev *dev)
1695 {
1696         unmap_internal_clock(dev);
1697         unmap_bf_area(dev);
1698         if (mlx4_is_slave(dev))
1699                 mlx4_slave_exit(dev);
1700         else {
1701                 mlx4_CLOSE_HCA(dev, 0);
1702                 mlx4_free_icms(dev);
1703         }
1704 }
1705
1706 static void mlx4_close_fw(struct mlx4_dev *dev)
1707 {
1708         if (!mlx4_is_slave(dev)) {
1709                 mlx4_UNMAP_FA(dev);
1710                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1711         }
1712 }
1713
1714 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1715 {
1716         panic("Disabled");
1717 #if 0 // AKAROS_PORT
1718 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1719
1720         uint32_t comm_flags;
1721         uint32_t offline_bit;
1722         unsigned long end;
1723         struct mlx4_priv *priv = mlx4_priv(dev);
1724
1725         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1726         while (time_before(jiffies, end)) {
1727                 comm_flags = swab32(read32((__iomem char *)priv->mfunc.comm +
1728                                            MLX4_COMM_CHAN_FLAGS));
1729                 offline_bit = (comm_flags &
1730                                (uint32_t)(1 << COMM_CHAN_OFFLINE_OFFSET));
1731                 if (!offline_bit)
1732                         return 0;
1733                 /* There are cases as part of AER/Reset flow that PF needs
1734                  * around 100 msec to load. We therefore sleep for 100 msec
1735                  * to allow other tasks to make use of that CPU during this
1736                  * time interval.
1737                  */
1738                 kthread_usleep(1000 * 100);
1739         }
1740         mlx4_err(dev, "Communication channel is offline.\n");
1741         return -EIO;
1742 #endif
1743 }
1744
1745 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1746 {
1747 #define COMM_CHAN_RST_OFFSET 0x1e
1748
1749         struct mlx4_priv *priv = mlx4_priv(dev);
1750         uint32_t comm_rst;
1751         uint32_t comm_caps;
1752
1753         comm_caps = swab32(read32((__iomem uint32_t*)priv->mfunc.comm +
1754                                   MLX4_COMM_CHAN_CAPS));
1755         comm_rst = (comm_caps & (uint32_t)(1 << COMM_CHAN_RST_OFFSET));
1756
1757         if (comm_rst)
1758                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1759 }
1760
1761 static int mlx4_init_slave(struct mlx4_dev *dev)
1762 {
1763         struct mlx4_priv *priv = mlx4_priv(dev);
1764         uint64_t dma = (uint64_t) priv->mfunc.vhcr_dma;
1765         int ret_from_reset = 0;
1766         uint32_t slave_read;
1767         uint32_t cmd_channel_ver;
1768
1769         if (atomic_read(&pf_loading)) {
1770                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1771                 return -EPROBE_DEFER;
1772         }
1773
1774         qlock(&priv->cmd.slave_cmd_mutex);
1775         priv->cmd.max_cmds = 1;
1776         if (mlx4_comm_check_offline(dev)) {
1777                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1778                 goto err_offline;
1779         }
1780
1781         mlx4_reset_vf_support(dev);
1782         mlx4_warn(dev, "Sending reset\n");
1783         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1784                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1785         /* if we are in the middle of flr the slave will try
1786          * NUM_OF_RESET_RETRIES times before leaving.*/
1787         if (ret_from_reset) {
1788                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1789                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1790                         qunlock(&priv->cmd.slave_cmd_mutex);
1791                         return -EPROBE_DEFER;
1792                 } else
1793                         goto err;
1794         }
1795
1796         /* check the driver version - the slave I/F revision
1797          * must match the master's */
1798         slave_read = swab32(read32(&priv->mfunc.comm->slave_read));
1799         cmd_channel_ver = mlx4_comm_get_version();
1800
1801         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1802                 MLX4_COMM_GET_IF_REV(slave_read)) {
1803                 mlx4_err(dev, "slave driver version is not supported by the master\n");
1804                 goto err;
1805         }
1806
1807         mlx4_warn(dev, "Sending vhcr0\n");
1808         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1809                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1810                 goto err;
1811         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1812                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1813                 goto err;
1814         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1815                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1816                 goto err;
1817         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1818                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1819                 goto err;
1820
1821         qunlock(&priv->cmd.slave_cmd_mutex);
1822         return 0;
1823
1824 err:
1825         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
1826 err_offline:
1827         qunlock(&priv->cmd.slave_cmd_mutex);
1828         return -EIO;
1829 }
1830
1831 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1832 {
1833         int i;
1834
1835         for (i = 1; i <= dev->caps.num_ports; i++) {
1836                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1837                         dev->caps.gid_table_len[i] =
1838                                 mlx4_get_slave_num_gids(dev, 0, i);
1839                 else
1840                         dev->caps.gid_table_len[i] = 1;
1841                 dev->caps.pkey_table_len[i] =
1842                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1843         }
1844 }
1845
1846 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1847 {
1848         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1849
1850         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1851               i++) {
1852                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1853                         break;
1854         }
1855
1856         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1857 }
1858
1859 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1860 {
1861         switch (dmfs_high_steer_mode) {
1862         case MLX4_STEERING_DMFS_A0_DEFAULT:
1863                 return "default performance";
1864
1865         case MLX4_STEERING_DMFS_A0_DYNAMIC:
1866                 return "dynamic hybrid mode";
1867
1868         case MLX4_STEERING_DMFS_A0_STATIC:
1869                 return "performance optimized for limited rule configuration (static)";
1870
1871         case MLX4_STEERING_DMFS_A0_DISABLE:
1872                 return "disabled performance optimized steering";
1873
1874         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1875                 return "performance optimized steering not supported";
1876
1877         default:
1878                 return "Unrecognized mode";
1879         }
1880 }
1881
1882 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
1883
1884 static void choose_steering_mode(struct mlx4_dev *dev,
1885                                  struct mlx4_dev_cap *dev_cap)
1886 {
1887         if (mlx4_log_num_mgm_entry_size <= 0) {
1888                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1889                         if (dev->caps.dmfs_high_steer_mode ==
1890                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1891                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
1892                         else
1893                                 dev->caps.dmfs_high_steer_mode =
1894                                         MLX4_STEERING_DMFS_A0_STATIC;
1895                 }
1896         }
1897
1898         if (mlx4_log_num_mgm_entry_size <= 0 &&
1899             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1900             (!mlx4_is_mfunc(dev) ||
1901              (dev_cap->fs_max_num_qp_per_entry >=
1902              (dev->persist->num_vfs + 1))) &&
1903             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1904                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1905                 dev->oper_log_mgm_entry_size =
1906                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1907                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1908                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1909                 dev->caps.fs_log_max_ucast_qp_range_size =
1910                         dev_cap->fs_log_max_ucast_qp_range_size;
1911         } else {
1912                 if (dev->caps.dmfs_high_steer_mode !=
1913                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1914                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
1915                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1916                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1917                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1918                 else {
1919                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1920
1921                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1922                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1923                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1924                 }
1925                 dev->oper_log_mgm_entry_size =
1926                         mlx4_log_num_mgm_entry_size > 0 ?
1927                         mlx4_log_num_mgm_entry_size :
1928                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1929                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1930         }
1931         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1932                  mlx4_steering_mode_str(dev->caps.steering_mode),
1933                  dev->oper_log_mgm_entry_size,
1934                  mlx4_log_num_mgm_entry_size);
1935 }
1936
1937 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1938                                        struct mlx4_dev_cap *dev_cap)
1939 {
1940         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1941             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1942                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1943         else
1944                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1945
1946         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
1947                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1948 }
1949
1950 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1951 {
1952         int i;
1953         struct mlx4_port_cap port_cap;
1954
1955         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1956                 return -EINVAL;
1957
1958         for (i = 1; i <= dev->caps.num_ports; i++) {
1959                 if (mlx4_dev_port(dev, i, &port_cap)) {
1960                         mlx4_err(dev,
1961                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1962                 } else if ((dev->caps.dmfs_high_steer_mode !=
1963                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
1964                            (port_cap.dmfs_optimized_state ==
1965                             !!(dev->caps.dmfs_high_steer_mode ==
1966                             MLX4_STEERING_DMFS_A0_DISABLE))) {
1967                         mlx4_err(dev,
1968                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1969                                  dmfs_high_rate_steering_mode_str(
1970                                         dev->caps.dmfs_high_steer_mode),
1971                                  (port_cap.dmfs_optimized_state ?
1972                                         "enabled" : "disabled"));
1973                 }
1974         }
1975
1976         return 0;
1977 }
1978
1979 static int mlx4_init_fw(struct mlx4_dev *dev)
1980 {
1981         struct mlx4_mod_stat_cfg   mlx4_cfg;
1982         int err = 0;
1983
1984         if (!mlx4_is_slave(dev)) {
1985                 err = mlx4_QUERY_FW(dev);
1986                 if (err) {
1987                         if (err == -EACCES)
1988                                 mlx4_info(dev, "non-primary physical function, skipping\n");
1989                         else
1990                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
1991                         return err;
1992                 }
1993
1994                 err = mlx4_load_fw(dev);
1995                 if (err) {
1996                         mlx4_err(dev, "Failed to start FW, aborting\n");
1997                         return err;
1998                 }
1999
2000                 mlx4_cfg.log_pg_sz_m = 1;
2001                 mlx4_cfg.log_pg_sz = 0;
2002                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2003                 if (err)
2004                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2005         }
2006
2007         return err;
2008 }
2009
2010 static int mlx4_init_hca(struct mlx4_dev *dev)
2011 {
2012         struct mlx4_priv          *priv = mlx4_priv(dev);
2013         struct mlx4_adapter        adapter;
2014         struct mlx4_dev_cap        dev_cap;
2015         struct mlx4_profile        profile;
2016         struct mlx4_init_hca_param init_hca;
2017         uint64_t icm_size;
2018         struct mlx4_config_dev_params params;
2019         int err;
2020
2021         if (!mlx4_is_slave(dev)) {
2022                 err = mlx4_dev_cap(dev, &dev_cap);
2023                 if (err) {
2024                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2025                         return err;
2026                 }
2027
2028                 choose_steering_mode(dev, &dev_cap);
2029                 choose_tunnel_offload_mode(dev, &dev_cap);
2030
2031                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2032                     mlx4_is_master(dev))
2033                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2034
2035                 err = mlx4_get_phys_port_id(dev);
2036                 if (err)
2037                         mlx4_err(dev, "Fail to get physical port id\n");
2038
2039                 if (mlx4_is_master(dev))
2040                         mlx4_parav_master_pf_caps(dev);
2041
2042                 if (mlx4_low_memory_profile()) {
2043                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2044                         profile = low_mem_profile;
2045                 } else {
2046                         profile = default_profile;
2047                 }
2048                 if (dev->caps.steering_mode ==
2049                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2050                         profile.num_mcg = MLX4_FS_NUM_MCG;
2051
2052                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2053                                              &init_hca);
2054                 if ((long long) icm_size < 0) {
2055                         err = icm_size;
2056                         return err;
2057                 }
2058
2059                 dev->caps.max_fmr_maps = (1 << (32 - LOG2_UP(dev->caps.num_mpts))) - 1;
2060
2061                 init_hca.log_uar_sz = LOG2_UP(dev->caps.num_uars);
2062                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2063                 init_hca.mw_enabled = 0;
2064                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2065                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2066                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2067
2068                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2069                 if (err)
2070                         return err;
2071
2072                 err = mlx4_INIT_HCA(dev, &init_hca);
2073                 if (err) {
2074                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2075                         goto err_free_icm;
2076                 }
2077
2078                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2079                         err = mlx4_query_func(dev, &dev_cap);
2080                         if (err < 0) {
2081                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2082                                 goto err_close;
2083                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2084                                 dev->caps.num_eqs = dev_cap.max_eqs;
2085                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2086                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2087                         }
2088                 }
2089
2090                 /*
2091                  * If TS is supported by FW
2092                  * read HCA frequency by QUERY_HCA command
2093                  */
2094                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2095                         memset(&init_hca, 0, sizeof(init_hca));
2096                         err = mlx4_QUERY_HCA(dev, &init_hca);
2097                         if (err) {
2098                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2099                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2100                         } else {
2101                                 dev->caps.hca_core_clock =
2102                                         init_hca.hca_core_clock;
2103                         }
2104
2105                         /* In case we got HCA frequency 0 - disable timestamping
2106                          * to avoid dividing by zero
2107                          */
2108                         if (!dev->caps.hca_core_clock) {
2109                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2110                                 mlx4_err(dev,
2111                                          "HCA frequency is 0 - timestamping is not supported\n");
2112                         } else if (map_internal_clock(dev)) {
2113                                 /*
2114                                  * Map internal clock,
2115                                  * in case of failure disable timestamping
2116                                  */
2117                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2118                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2119                         }
2120                 }
2121
2122                 if (dev->caps.dmfs_high_steer_mode !=
2123                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2124                         if (mlx4_validate_optimized_steering(dev))
2125                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2126
2127                         if (dev->caps.dmfs_high_steer_mode ==
2128                             MLX4_STEERING_DMFS_A0_DISABLE) {
2129                                 dev->caps.dmfs_high_rate_qpn_base =
2130                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2131                                 dev->caps.dmfs_high_rate_qpn_range =
2132                                         MLX4_A0_STEERING_TABLE_SIZE;
2133                         }
2134
2135                         mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2136                                  dmfs_high_rate_steering_mode_str(
2137                                         dev->caps.dmfs_high_steer_mode));
2138                 }
2139         } else {
2140                 err = mlx4_init_slave(dev);
2141                 if (err) {
2142                         if (err != -EPROBE_DEFER)
2143                                 mlx4_err(dev, "Failed to initialize slave\n");
2144                         return err;
2145                 }
2146
2147                 err = mlx4_slave_cap(dev);
2148                 if (err) {
2149                         mlx4_err(dev, "Failed to obtain slave caps\n");
2150                         goto err_close;
2151                 }
2152         }
2153
2154 #if 0 // AKAROS_PORT
2155         if (map_bf_area(dev))
2156                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2157 #endif
2158
2159         /*Only the master set the ports, all the rest got it from it.*/
2160         if (!mlx4_is_slave(dev))
2161                 mlx4_set_port_mask(dev);
2162
2163         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2164         if (err) {
2165                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2166                 goto unmap_bf;
2167         }
2168
2169         /* Query CONFIG_DEV parameters */
2170         err = mlx4_config_dev_retrieval(dev, &params);
2171         if (err && err != -ENOTSUPP) {
2172                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2173         } else if (!err) {
2174                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2175                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2176         }
2177         priv->eq_table.inta_pin = adapter.inta_pin;
2178         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2179
2180         return 0;
2181
2182 unmap_bf:
2183         unmap_internal_clock(dev);
2184         unmap_bf_area(dev);
2185
2186         if (mlx4_is_slave(dev)) {
2187                 kfree(dev->caps.qp0_qkey);
2188                 kfree(dev->caps.qp0_tunnel);
2189                 kfree(dev->caps.qp0_proxy);
2190                 kfree(dev->caps.qp1_tunnel);
2191                 kfree(dev->caps.qp1_proxy);
2192         }
2193
2194 err_close:
2195         if (mlx4_is_slave(dev))
2196                 mlx4_slave_exit(dev);
2197         else
2198                 mlx4_CLOSE_HCA(dev, 0);
2199
2200 err_free_icm:
2201         if (!mlx4_is_slave(dev))
2202                 mlx4_free_icms(dev);
2203
2204         return err;
2205 }
2206
2207 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2208 {
2209         struct mlx4_priv *priv = mlx4_priv(dev);
2210         int nent;
2211
2212         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2213                 return -ENOENT;
2214
2215         nent = dev->caps.max_counters;
2216         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
2217 }
2218
2219 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2220 {
2221         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2222 }
2223
2224 int __mlx4_counter_alloc(struct mlx4_dev *dev, uint32_t *idx)
2225 {
2226         struct mlx4_priv *priv = mlx4_priv(dev);
2227
2228         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2229                 return -ENOENT;
2230
2231         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2232         if (*idx == -1)
2233                 return -ENOMEM;
2234
2235         return 0;
2236 }
2237
2238 int mlx4_counter_alloc(struct mlx4_dev *dev, uint32_t *idx)
2239 {
2240         uint64_t out_param;
2241         int err;
2242
2243         if (mlx4_is_mfunc(dev)) {
2244                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2245                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2246                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2247                 if (!err)
2248                         *idx = get_param_l(&out_param);
2249
2250                 return err;
2251         }
2252         return __mlx4_counter_alloc(dev, idx);
2253 }
2254 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2255
2256 void __mlx4_counter_free(struct mlx4_dev *dev, uint32_t idx)
2257 {
2258         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2259         return;
2260 }
2261
2262 void mlx4_counter_free(struct mlx4_dev *dev, uint32_t idx)
2263 {
2264         uint64_t in_param = 0;
2265
2266         if (mlx4_is_mfunc(dev)) {
2267                 set_param_l(&in_param, idx);
2268                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2269                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2270                          MLX4_CMD_WRAPPED);
2271                 return;
2272         }
2273         __mlx4_counter_free(dev, idx);
2274 }
2275 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2276
2277 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2278 {
2279         struct mlx4_priv *priv = mlx4_priv(dev);
2280
2281         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2282 }
2283 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2284
2285 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2286 {
2287         struct mlx4_priv *priv = mlx4_priv(dev);
2288
2289         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2290 }
2291 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2292
2293 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2294 {
2295         struct mlx4_priv *priv = mlx4_priv(dev);
2296         __be64 guid;
2297
2298         /* hw GUID */
2299         if (entry == 0)
2300                 return;
2301
2302         get_random_bytes((char *)&guid, sizeof(guid));
2303         guid &= ~(cpu_to_be64(1ULL << 56));
2304         guid |= cpu_to_be64(1ULL << 57);
2305         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2306 }
2307
2308 static int mlx4_setup_hca(struct mlx4_dev *dev)
2309 {
2310         struct mlx4_priv *priv = mlx4_priv(dev);
2311         int err;
2312         int port;
2313         __be32 ib_port_default_caps;
2314
2315         err = mlx4_init_uar_table(dev);
2316         if (err) {
2317                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2318                  return err;
2319         }
2320
2321         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2322         if (err) {
2323                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2324                 goto err_uar_table_free;
2325         }
2326
2327         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2328         if (!priv->kar) {
2329                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2330                 err = -ENOMEM;
2331                 goto err_uar_free;
2332         }
2333
2334         err = mlx4_init_pd_table(dev);
2335         if (err) {
2336                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2337                 goto err_kar_unmap;
2338         }
2339
2340         err = mlx4_init_xrcd_table(dev);
2341         if (err) {
2342                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2343                 goto err_pd_table_free;
2344         }
2345
2346         err = mlx4_init_mr_table(dev);
2347         if (err) {
2348                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2349                 goto err_xrcd_table_free;
2350         }
2351
2352         if (!mlx4_is_slave(dev)) {
2353                 err = mlx4_init_mcg_table(dev);
2354                 if (err) {
2355                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2356                         goto err_mr_table_free;
2357                 }
2358                 err = mlx4_config_mad_demux(dev);
2359                 if (err) {
2360                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2361                         goto err_mcg_table_free;
2362                 }
2363         }
2364
2365         err = mlx4_init_eq_table(dev);
2366         if (err) {
2367                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2368                 goto err_mcg_table_free;
2369         }
2370
2371         err = mlx4_cmd_use_events(dev);
2372         if (err) {
2373                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2374                 goto err_eq_table_free;
2375         }
2376
2377         err = mlx4_NOP(dev);
2378         if (err) {
2379                 if (dev->flags & MLX4_FLAG_MSI_X) {
2380                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2381                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2382                         panic("MSI-X required");
2383                         mlx4_warn(dev, "Trying again without MSI-X\n");
2384                 } else {
2385                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2386                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2387                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2388                 }
2389
2390                 goto err_cmd_poll;
2391         }
2392
2393         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2394
2395         err = mlx4_init_cq_table(dev);
2396         if (err) {
2397                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2398                 goto err_cmd_poll;
2399         }
2400
2401         err = mlx4_init_srq_table(dev);
2402         if (err) {
2403                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2404                 goto err_cq_table_free;
2405         }
2406
2407         err = mlx4_init_qp_table(dev);
2408         if (err) {
2409                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2410                 goto err_srq_table_free;
2411         }
2412
2413         err = mlx4_init_counters_table(dev);
2414         if (err && err != -ENOENT) {
2415                 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2416                 goto err_qp_table_free;
2417         }
2418
2419         if (!mlx4_is_slave(dev)) {
2420                 for (port = 1; port <= dev->caps.num_ports; port++) {
2421                         ib_port_default_caps = 0;
2422                         err = mlx4_get_port_ib_caps(dev, port,
2423                                                     &ib_port_default_caps);
2424                         if (err)
2425                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2426                                           port, err);
2427                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2428
2429                         /* initialize per-slave default ib port capabilities */
2430                         if (mlx4_is_master(dev)) {
2431                                 int i;
2432                                 for (i = 0; i < dev->num_slaves; i++) {
2433                                         if (i == mlx4_master_func_num(dev))
2434                                                 continue;
2435                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2436                                                 ib_port_default_caps;
2437                                 }
2438                         }
2439
2440                         if (mlx4_is_mfunc(dev))
2441                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2442                         else
2443                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2444
2445                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2446                                             dev->caps.pkey_table_len[port] : -1);
2447                         if (err) {
2448                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2449                                          port);
2450                                 goto err_counters_table_free;
2451                         }
2452                 }
2453         }
2454
2455         return 0;
2456
2457 err_counters_table_free:
2458         mlx4_cleanup_counters_table(dev);
2459
2460 err_qp_table_free:
2461         mlx4_cleanup_qp_table(dev);
2462
2463 err_srq_table_free:
2464         mlx4_cleanup_srq_table(dev);
2465
2466 err_cq_table_free:
2467         mlx4_cleanup_cq_table(dev);
2468
2469 err_cmd_poll:
2470         mlx4_cmd_use_polling(dev);
2471
2472 err_eq_table_free:
2473         mlx4_cleanup_eq_table(dev);
2474
2475 err_mcg_table_free:
2476         if (!mlx4_is_slave(dev))
2477                 mlx4_cleanup_mcg_table(dev);
2478
2479 err_mr_table_free:
2480         mlx4_cleanup_mr_table(dev);
2481
2482 err_xrcd_table_free:
2483         mlx4_cleanup_xrcd_table(dev);
2484
2485 err_pd_table_free:
2486         mlx4_cleanup_pd_table(dev);
2487
2488 err_kar_unmap:
2489         iounmap(priv->kar);
2490
2491 err_uar_free:
2492         mlx4_uar_free(dev, &priv->driver_uar);
2493
2494 err_uar_table_free:
2495         mlx4_cleanup_uar_table(dev);
2496         return err;
2497 }
2498
2499 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2500 {
2501 #if 0 // AKAROS_PORT
2502         struct mlx4_priv *priv = mlx4_priv(dev);
2503         struct msix_entry *entries;
2504         int i;
2505
2506         if (msi_x) {
2507                 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2508
2509                 nreq = MIN_T(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2510                              nreq);
2511
2512                 entries = kzmalloc((nreq) * (sizeof *entries), MEM_WAIT);
2513                 if (!entries)
2514                         goto no_msi;
2515
2516                 for (i = 0; i < nreq; ++i)
2517                         entries[i].entry = i;
2518
2519                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2520                                              nreq);
2521
2522                 if (nreq < 0) {
2523                         kfree(entries);
2524                         goto no_msi;
2525                 } else if (nreq < MSIX_LEGACY_SZ +
2526                            dev->caps.num_ports * MIN_MSIX_P_PORT) {
2527                         /*Working in legacy mode , all EQ's shared*/
2528                         dev->caps.comp_pool           = 0;
2529                         dev->caps.num_comp_vectors = nreq - 1;
2530                 } else {
2531                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
2532                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2533                 }
2534                 for (i = 0; i < nreq; ++i)
2535                         priv->eq_table.eq[i].irq = entries[i].vector;
2536
2537                 dev->flags |= MLX4_FLAG_MSI_X;
2538
2539                 kfree(entries);
2540                 return;
2541         }
2542
2543 no_msi:
2544         dev->caps.num_comp_vectors = 1;
2545         dev->caps.comp_pool        = 0;
2546
2547         for (i = 0; i < 2; ++i)
2548                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2549 #else
2550         if (!msi_x)
2551                 panic("!msi_x");
2552
2553         if (pci_msix_init(dev->persist->pdev) == -1)
2554                 panic("pci_msix_init -1");
2555
2556         dev->caps.comp_pool = 0;
2557         dev->caps.num_comp_vectors = 1;
2558
2559         dev->flags |= MLX4_FLAG_MSI_X;
2560 #endif
2561 }
2562
2563 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2564 {
2565         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2566         int err = 0;
2567
2568         info->dev = dev;
2569         info->port = port;
2570         if (!mlx4_is_slave(dev)) {
2571                 mlx4_init_mac_table(dev, &info->mac_table);
2572                 mlx4_init_vlan_table(dev, &info->vlan_table);
2573                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2574                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2575         }
2576
2577         sprintf(info->dev_name, "mlx4_port%d", port);
2578 #if 0 // AKAROS_PORT
2579         info->port_attr.attr.name = info->dev_name;
2580         if (mlx4_is_mfunc(dev))
2581                 info->port_attr.attr.mode = S_IRUGO;
2582         else {
2583                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2584                 info->port_attr.store     = set_port_type;
2585         }
2586         info->port_attr.show      = show_port_type;
2587         sysfs_attr_init(&info->port_attr.attr);
2588
2589         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2590         if (err) {
2591                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2592                 info->port = -1;
2593         }
2594 #endif
2595
2596         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2597 #if 0 // AKAROS_PORT
2598         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2599         if (mlx4_is_mfunc(dev))
2600                 info->port_mtu_attr.attr.mode = S_IRUGO;
2601         else {
2602                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2603                 info->port_mtu_attr.store     = set_port_ib_mtu;
2604         }
2605         info->port_mtu_attr.show      = show_port_ib_mtu;
2606         sysfs_attr_init(&info->port_mtu_attr.attr);
2607
2608         err = device_create_file(&dev->persist->pdev->dev,
2609                                  &info->port_mtu_attr);
2610         if (err) {
2611                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2612                 device_remove_file(&info->dev->persist->pdev->dev,
2613                                    &info->port_attr);
2614                 info->port = -1;
2615         }
2616 #endif
2617
2618         return err;
2619 }
2620
2621 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2622 {
2623         panic("Disabled");
2624 #if 0 // AKAROS_PORT
2625         if (info->port < 0)
2626                 return;
2627
2628         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2629         device_remove_file(&info->dev->persist->pdev->dev,
2630                            &info->port_mtu_attr);
2631 #endif
2632 }
2633
2634 static int mlx4_init_steering(struct mlx4_dev *dev)
2635 {
2636         struct mlx4_priv *priv = mlx4_priv(dev);
2637         int num_entries = dev->caps.num_ports;
2638         int i, j;
2639
2640         priv->steer = kzmalloc(sizeof(struct mlx4_steer) * num_entries,
2641                                MEM_WAIT);
2642         if (!priv->steer)
2643                 return -ENOMEM;
2644
2645         for (i = 0; i < num_entries; i++)
2646                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2647                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2648                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2649                 }
2650         return 0;
2651 }
2652
2653 static void mlx4_clear_steering(struct mlx4_dev *dev)
2654 {
2655         struct mlx4_priv *priv = mlx4_priv(dev);
2656         struct mlx4_steer_index *entry, *tmp_entry;
2657         struct mlx4_promisc_qp *pqp, *tmp_pqp;
2658         int num_entries = dev->caps.num_ports;
2659         int i, j;
2660
2661         for (i = 0; i < num_entries; i++) {
2662                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2663                         list_for_each_entry_safe(pqp, tmp_pqp,
2664                                                  &priv->steer[i].promisc_qps[j],
2665                                                  list) {
2666                                 list_del(&pqp->list);
2667                                 kfree(pqp);
2668                         }
2669                         list_for_each_entry_safe(entry, tmp_entry,
2670                                                  &priv->steer[i].steer_entries[j],
2671                                                  list) {
2672                                 list_del(&entry->list);
2673                                 list_for_each_entry_safe(pqp, tmp_pqp,
2674                                                          &entry->duplicates,
2675                                                          list) {
2676                                         list_del(&pqp->list);
2677                                         kfree(pqp);
2678                                 }
2679                                 kfree(entry);
2680                         }
2681                 }
2682         }
2683         kfree(priv->steer);
2684 }
2685
2686 #if 0 // AKAROS_PORT
2687 static int extended_func_num(struct pci_device *pdev)
2688 {
2689         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2690 }
2691 #endif
2692
2693 #define MLX4_OWNER_BASE 0x8069c
2694 #define MLX4_OWNER_SIZE 4
2695
2696 static int mlx4_get_ownership(struct mlx4_dev *dev)
2697 {
2698         void __iomem *owner;
2699         uint32_t ret;
2700
2701         if (pci_channel_offline(dev->persist->pdev))
2702                 return -EIO;
2703
2704         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2705                         MLX4_OWNER_BASE,
2706                         MLX4_OWNER_SIZE);
2707         if (!owner) {
2708                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2709                 return -ENOMEM;
2710         }
2711
2712         ret = read32(owner);
2713         iounmap(owner);
2714         return (int) !!ret;
2715 }
2716
2717 static void mlx4_free_ownership(struct mlx4_dev *dev)
2718 {
2719         void __iomem *owner;
2720
2721         if (pci_channel_offline(dev->persist->pdev))
2722                 return;
2723
2724         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2725                         MLX4_OWNER_BASE,
2726                         MLX4_OWNER_SIZE);
2727         if (!owner) {
2728                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2729                 return;
2730         }
2731         write32(0, owner);
2732         kthread_usleep(1000 * 1000);
2733         iounmap(owner);
2734 }
2735
2736 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2737                                   !!((flags) & MLX4_FLAG_MASTER))
2738
2739 static uint64_t mlx4_enable_sriov(struct mlx4_dev *dev,
2740                                   struct pci_device *pdev,
2741                                   uint8_t total_vfs, int existing_vfs,
2742                                   int reset_flow)
2743 {
2744         panic("Disabled");
2745 #if 0 // AKAROS_PORT
2746         uint64_t dev_flags = dev->flags;
2747         int err = 0;
2748
2749         if (reset_flow) {
2750                 dev->dev_vfs = kzmalloc((total_vfs) * (sizeof(*dev->dev_vfs)),
2751                                         MEM_WAIT);
2752                 if (!dev->dev_vfs)
2753                         goto free_mem;
2754                 return dev_flags;
2755         }
2756
2757         atomic_inc(&pf_loading);
2758         if (dev->flags &  MLX4_FLAG_SRIOV) {
2759                 if (existing_vfs != total_vfs) {
2760                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2761                                  existing_vfs, total_vfs);
2762                         total_vfs = existing_vfs;
2763                 }
2764         }
2765
2766         dev->dev_vfs = kzmalloc(total_vfs * sizeof(*dev->dev_vfs),
2767                                 MEM_WAIT);
2768         if (NULL == dev->dev_vfs) {
2769                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2770                 goto disable_sriov;
2771         }
2772
2773         if (!(dev->flags &  MLX4_FLAG_SRIOV)) {
2774                 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2775                 err = pci_enable_sriov(pdev, total_vfs);
2776         }
2777         if (err) {
2778                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2779                          err);
2780                 goto disable_sriov;
2781         } else {
2782                 mlx4_warn(dev, "Running in master mode\n");
2783                 dev_flags |= MLX4_FLAG_SRIOV |
2784                         MLX4_FLAG_MASTER;
2785                 dev_flags &= ~MLX4_FLAG_SLAVE;
2786                 dev->persist->num_vfs = total_vfs;
2787         }
2788         return dev_flags;
2789
2790 disable_sriov:
2791         atomic_dec(&pf_loading);
2792 free_mem:
2793         dev->persist->num_vfs = 0;
2794         kfree(dev->dev_vfs);
2795         return dev_flags & ~MLX4_FLAG_MASTER;
2796 #endif
2797 }
2798
2799 enum {
2800         MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2801 };
2802
2803 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2804                               int *nvfs)
2805 {
2806         int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2807         /* Checking for 64 VFs as a limitation of CX2 */
2808         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2809             requested_vfs >= 64) {
2810                 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2811                          requested_vfs);
2812                 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2813         }
2814         return 0;
2815 }
2816
2817 static int mlx4_load_one(struct pci_device *pdev, int pci_dev_data,
2818                          int total_vfs, int *nvfs, struct mlx4_priv *priv,
2819                          int reset_flow)
2820 {
2821         struct mlx4_dev *dev;
2822         unsigned sum = 0;
2823         int err;
2824         int port;
2825         int i;
2826         struct mlx4_dev_cap *dev_cap = NULL;
2827         int existing_vfs = 0;
2828
2829         dev = &priv->dev;
2830
2831         INIT_LIST_HEAD(&priv->ctx_list);
2832         spinlock_init_irqsave(&priv->ctx_lock);
2833
2834         qlock_init(&priv->port_mutex);
2835         qlock_init(&priv->bond_mutex);
2836
2837         INIT_LIST_HEAD(&priv->pgdir_list);
2838         qlock_init(&priv->pgdir_mutex);
2839
2840         INIT_LIST_HEAD(&priv->bf_list);
2841         qlock_init(&priv->bf_mutex);
2842
2843 #if 0 // AKAROS_PORT
2844         dev->rev_id = pdev->revision;
2845 #endif
2846         dev->numa_node = dev_to_node(&pdev->dev);
2847
2848         /* Detect if this device is a virtual function */
2849         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2850                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2851                 dev->flags |= MLX4_FLAG_SLAVE;
2852         } else {
2853                 /* We reset the device and enable SRIOV only for physical
2854                  * devices.  Try to claim ownership on the device;
2855                  * if already taken, skip -- do not allow multiple PFs */
2856                 err = mlx4_get_ownership(dev);
2857                 if (err) {
2858                         if (err < 0)
2859                                 return err;
2860                         else {
2861                                 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
2862                                 return -EINVAL;
2863                         }
2864                 }
2865
2866                 atomic_set(&priv->opreq_count, 0);
2867                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2868
2869                 /*
2870                  * Now reset the HCA before we touch the PCI capabilities or
2871                  * attempt a firmware command, since a boot ROM may have left
2872                  * the HCA in an undefined state.
2873                  */
2874                 err = mlx4_reset(dev);
2875                 if (err) {
2876                         mlx4_err(dev, "Failed to reset HCA, aborting\n");
2877                         goto err_sriov;
2878                 }
2879
2880 #if 0 // AKAROS_PORT
2881                 if (total_vfs) {
2882                         dev->flags = MLX4_FLAG_MASTER;
2883                         existing_vfs = pci_num_vf(pdev);
2884                         if (existing_vfs)
2885                                 dev->flags |= MLX4_FLAG_SRIOV;
2886                         dev->persist->num_vfs = total_vfs;
2887                 }
2888 #endif
2889         }
2890
2891         /* on load remove any previous indication of internal error,
2892          * device is up.
2893          */
2894         dev->persist->state = MLX4_DEVICE_STATE_UP;
2895
2896 slave_start:
2897         err = mlx4_cmd_init(dev);
2898         if (err) {
2899                 mlx4_err(dev, "Failed to init command interface, aborting\n");
2900                 goto err_sriov;
2901         }
2902
2903         /* In slave functions, the communication channel must be initialized
2904          * before posting commands. Also, init num_slaves before calling
2905          * mlx4_init_hca */
2906         if (mlx4_is_mfunc(dev)) {
2907                 if (mlx4_is_master(dev)) {
2908                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2909
2910                 } else {
2911                         dev->num_slaves = 0;
2912                         err = mlx4_multi_func_init(dev);
2913                         if (err) {
2914                                 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
2915                                 goto err_cmd;
2916                         }
2917                 }
2918         }
2919
2920         err = mlx4_init_fw(dev);
2921         if (err) {
2922                 mlx4_err(dev, "Failed to init fw, aborting.\n");
2923                 goto err_mfunc;
2924         }
2925
2926         if (mlx4_is_master(dev)) {
2927                 /* when we hit the goto slave_start below, dev_cap already initialized */
2928                 if (!dev_cap) {
2929                         dev_cap = kzmalloc(sizeof(*dev_cap), MEM_WAIT);
2930
2931                         if (!dev_cap) {
2932                                 err = -ENOMEM;
2933                                 goto err_fw;
2934                         }
2935
2936                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2937                         if (err) {
2938                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2939                                 goto err_fw;
2940                         }
2941
2942                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2943                                 goto err_fw;
2944
2945                         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2946                                 uint64_t dev_flags = mlx4_enable_sriov(dev, pdev,
2947                                                                   total_vfs,
2948                                                                   existing_vfs,
2949                                                                   reset_flow);
2950
2951                                 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2952                                 dev->flags = dev_flags;
2953                                 if (!SRIOV_VALID_STATE(dev->flags)) {
2954                                         mlx4_err(dev, "Invalid SRIOV state\n");
2955                                         goto err_sriov;
2956                                 }
2957                                 err = mlx4_reset(dev);
2958                                 if (err) {
2959                                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2960                                         goto err_sriov;
2961                                 }
2962                                 goto slave_start;
2963                         }
2964                 } else {
2965                         /* Legacy mode FW requires SRIOV to be enabled before
2966                          * doing QUERY_DEV_CAP, since max_eq's value is different if
2967                          * SRIOV is enabled.
2968                          */
2969                         memset(dev_cap, 0, sizeof(*dev_cap));
2970                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2971                         if (err) {
2972                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2973                                 goto err_fw;
2974                         }
2975
2976                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2977                                 goto err_fw;
2978                 }
2979         }
2980
2981         err = mlx4_init_hca(dev);
2982         if (err) {
2983                 if (err == -EACCES) {
2984                         /* Not primary Physical function
2985                          * Running in slave mode */
2986                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2987                         /* We're not a PF */
2988 #if 0 // AKAROS_PORT
2989                         if (dev->flags & MLX4_FLAG_SRIOV) {
2990                                 if (!existing_vfs)
2991                                         pci_disable_sriov(pdev);
2992                                 if (mlx4_is_master(dev) && !reset_flow)
2993                                         atomic_dec(&pf_loading);
2994                                 dev->flags &= ~MLX4_FLAG_SRIOV;
2995                         }
2996 #endif
2997                         if (!mlx4_is_slave(dev))
2998                                 mlx4_free_ownership(dev);
2999                         dev->flags |= MLX4_FLAG_SLAVE;
3000                         dev->flags &= ~MLX4_FLAG_MASTER;
3001                         goto slave_start;
3002                 } else
3003                         goto err_fw;
3004         }
3005
3006         if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3007                 uint64_t dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3008                                                   existing_vfs, reset_flow);
3009
3010                 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3011                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3012                         dev->flags = dev_flags;
3013                         err = mlx4_cmd_init(dev);
3014                         if (err) {
3015                                 /* Only VHCR is cleaned up, so could still
3016                                  * send FW commands
3017                                  */
3018                                 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3019                                 goto err_close;
3020                         }
3021                 } else {
3022                         dev->flags = dev_flags;
3023                 }
3024
3025                 if (!SRIOV_VALID_STATE(dev->flags)) {
3026                         mlx4_err(dev, "Invalid SRIOV state\n");
3027                         goto err_close;
3028                 }
3029         }
3030
3031         /* check if the device is functioning at its maximum possible speed.
3032          * No return code for this call, just warn the user in case of PCI
3033          * express device capabilities are under-satisfied by the bus.
3034          */
3035         if (!mlx4_is_slave(dev))
3036                 mlx4_check_pcie_caps(dev);
3037
3038         /* In master functions, the communication channel must be initialized
3039          * after obtaining its address from fw */
3040         if (mlx4_is_master(dev)) {
3041                 int ib_ports = 0;
3042
3043                 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3044                         ib_ports++;
3045
3046                 if (ib_ports &&
3047                     (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
3048                         mlx4_err(dev,
3049                                  "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
3050                         err = -EINVAL;
3051                         goto err_close;
3052                 }
3053                 if (dev->caps.num_ports < 2 &&
3054                     num_vfs_argc > 1) {
3055                         err = -EINVAL;
3056                         mlx4_err(dev,
3057                                  "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3058                                  dev->caps.num_ports);
3059                         goto err_close;
3060                 }
3061                 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3062
3063                 for (i = 0;
3064                      i < sizeof(dev->persist->nvfs)/
3065                      sizeof(dev->persist->nvfs[0]); i++) {
3066                         unsigned j;
3067
3068                         for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3069                                 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3070                                 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3071                                         dev->caps.num_ports;
3072                         }
3073                 }
3074
3075                 /* In master functions, the communication channel
3076                  * must be initialized after obtaining its address from fw
3077                  */
3078                 err = mlx4_multi_func_init(dev);
3079                 if (err) {
3080                         mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3081                         goto err_close;
3082                 }
3083         }
3084
3085         err = mlx4_alloc_eq_table(dev);
3086         if (err)
3087                 goto err_master_mfunc;
3088
3089         priv->msix_ctl.pool_bm = 0;
3090         qlock_init(&priv->msix_ctl.pool_lock);
3091
3092         mlx4_enable_msi_x(dev);
3093         if ((mlx4_is_mfunc(dev)) &&
3094             !(dev->flags & MLX4_FLAG_MSI_X)) {
3095                 err = -ENOSYS;
3096                 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3097                 goto err_free_eq;
3098         }
3099
3100         if (!mlx4_is_slave(dev)) {
3101                 err = mlx4_init_steering(dev);
3102                 if (err)
3103                         goto err_disable_msix;
3104         }
3105
3106         err = mlx4_setup_hca(dev);
3107 #if 0 // AKAROS_PORT
3108         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3109             !mlx4_is_mfunc(dev)) {
3110                 dev->flags &= ~MLX4_FLAG_MSI_X;
3111                 dev->caps.num_comp_vectors = 1;
3112                 dev->caps.comp_pool        = 0;
3113                 pci_disable_msix(pdev);
3114                 err = mlx4_setup_hca(dev);
3115         }
3116 #endif
3117
3118         if (err)
3119                 goto err_steer;
3120
3121         mlx4_init_quotas(dev);
3122         /* When PF resources are ready arm its comm channel to enable
3123          * getting commands
3124          */
3125         if (mlx4_is_master(dev)) {
3126                 err = mlx4_ARM_COMM_CHANNEL(dev);
3127                 if (err) {
3128                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3129                                  err);
3130                         goto err_steer;
3131                 }
3132         }
3133
3134         for (port = 1; port <= dev->caps.num_ports; port++) {
3135                 err = mlx4_init_port_info(dev, port);
3136                 if (err)
3137                         goto err_port;
3138         }
3139
3140         priv->v2p.port1 = 1;
3141         priv->v2p.port2 = 2;
3142
3143         err = mlx4_register_device(dev);
3144         if (err)
3145                 goto err_port;
3146
3147         mlx4_request_modules(dev);
3148
3149         mlx4_sense_init(dev);
3150         mlx4_start_sense(dev);
3151
3152         priv->removed = 0;
3153
3154         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3155                 atomic_dec(&pf_loading);
3156
3157         kfree(dev_cap);
3158         return 0;
3159
3160 err_port:
3161         for (--port; port >= 1; --port)
3162                 mlx4_cleanup_port_info(&priv->port[port]);
3163
3164         mlx4_cleanup_counters_table(dev);
3165         mlx4_cleanup_qp_table(dev);
3166         mlx4_cleanup_srq_table(dev);
3167         mlx4_cleanup_cq_table(dev);
3168         mlx4_cmd_use_polling(dev);
3169         mlx4_cleanup_eq_table(dev);
3170         mlx4_cleanup_mcg_table(dev);
3171         mlx4_cleanup_mr_table(dev);
3172         mlx4_cleanup_xrcd_table(dev);
3173         mlx4_cleanup_pd_table(dev);
3174         mlx4_cleanup_uar_table(dev);
3175
3176 err_steer:
3177         if (!mlx4_is_slave(dev))
3178                 mlx4_clear_steering(dev);
3179